This application claims priority to an application entitled xe2x80x9cCommunication Apparatus And Method for CDMA Communication Systemxe2x80x9d filed in the Korean Industrial Property Office on Jan. 21, 1999 and assigned Serial No. 99-2311, the contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates generally to a channel coding apparatus and method for a Code Division Multiple Access (CDMA) communication system, and in particular, to a channel coding apparatus and method for a DS (Direct Sequence)-CDMA communication system. Further, the present invention provides a channel decoding apparatus and method for receiving signals transmitted from a base station having the above channel coding apparatus.
2. Description of the Related Art
Current CDMA communication systems are implemented according to the IS-95 standard. With an increase in the sophistication of CDMA communication technology and a decrease in usage costs, there has been exponential growth in the number of subscribers to CDMA communication services. Accordingly, many methods have been proposed for meeting subscribers"" ever-increasing demands for high quality CDMA service. For example, several methods for improving the forward link structure in CDMA communication system have been proposed.
One such method for improving the forward link structure, especially the forward link fundamental channel designed for the third generation multicarrier CDMA system, was proposed in the TIA/EIA TR45.5 conference and approved on May 15, 1998 by the Telecommunications Industry Association (TIA). A forward link structure for a multicarrier CDMA communication system is illustrated in FIG. 1.
With reference to FIG. 1, a channel encoder 10 encodes input data, and a rate matcher 20 repeats and punctures symbols outputted from the channel encoder 10. Here, the data input to the channel encoder 10 has a variable bit rate. The rate matcher 20 repeats and punctures the coded data bits (i.e., symbols) outputted from the channel encoder 10 in order to match the symbol rates for variable bit rate data. A channel interleaver 30 interleaves an output of the rate matcher 20. A block interleaver is typically used for the interleaver 30.
A long code generator 91 generates a long code which uniquely identifies each subscriber. A decimator 92 decimates the long code to match the rate of the long code to the rate of the symbols outputted from the interleaver 30. An adder 93 mixes an output of the channel interleaver 30 and an output of the decimator 92. An exclusive OR gate is typically used for the adder 93.
A demultiplexer 40 sequentially demultiplexes data outputted from the adder 93 to multiple carriers A, B and C. First to third signal converters 51-53 convert signal levels of binary data outputted from the demultiplexer 40 by converting input data of xe2x80x980xe2x80x99 to xe2x80x98+1xe2x80x99 and input data of xe2x80x981xe2x80x99 to xe2x88x92xe2x80x981xe2x80x99. First to third Walsh encoders (or orthogonal modulators) 61-63 encode data outputted from the first to third signal converters 51-53, respectively, using corresponding Walsh codes. Here, the Walsh codes have a length of 256 bits. First to third modulators 71-73 modulate outputs of the first to third Walsh encoders 61-63, respectively. Here, QPSK (Quadrature Phase Shift Keying) spreaders can be used for the modulators 71-73. First to third attenuators (or gain controllers) 81-83 control gains of the modulated signals outputted from the first to third modulators 71-73 according to corresponding attenuation signals GA-GC, respectively. Here, the signals are outputted from the first to third attenuators 81-83 with different carriers A, B and C.
In the forward link structure of FIG. 1, the channel encoder 10, having a coding rate of R=1/3, encodes a single input data bit into 3 coded data bits (i.e., code words or symbols). Such coded data bits are demultiplexed to the three carriers A, B and C after rate matching and channel interleaving. That is, the multicarrier CDMA forward link of FIG. 1 encodes and interleaves the input data and then demultiplexes the data to the three carriers before transmission.
FIG. 1 shows a multicarrier CDMA communication system. This can be modified to a single-carrier CDMA communication system by removing the demultiplexer 40 and using a signal converter, an orthogonal modulator, a spreader and an attenuator for single carrier.
FIG. 2 is a detailed diagram illustrating the channel encoder 10, the rate matcher 20 and the channel interleaver 30. In FIG. 2, data at the first rate is composed of 172 bits (full rate) per 20 ms frame; data at the second rate is composed of 80 bits (1/2 rate) per 20 ms frame; data at the third rate is composed of 40 bits (1/4 rate) per 20 ms frame; and data at the fourth rate is composed of 16 bits (1/8 rate) per 20 ms frame.
First to fourth CRC (Cyclic Redundancy Code or Cyclic Redundancy Check) generators 111-114 generate CRC bits corresponding to the respective input data having different rates and add the generated CRC bits to the input data. Specifically, a 12-bit CRC is added to the 172-bit data of the first rate; an 8-bit CRC is added to the 80-bit data of the second rate; a 6-bit CRC is added to the 40-bit data of the third rate; and a 6-bit CRC is added to the 16-bit data of the fourth rate. First to fourth tail bit generators 121-124 add 8 tail bits to the CRC-added data, respectively. Therefore, the first tail bit generator 121 outputs 192 bits; the second tail bit generator 122 outputs 96 bits; the third tail bit generator 123 outputs 54 bits; and the fourth tail bit generator 124 outputs 30 bits.
First to fourth encoders 11-14 encode data output from the first to fourth tail bit generators 121-124, respectively. A convolutional encoder having a constraint length of K=9 and a coding rate of R=1/3 can be used for the encoders 11-14. In this case, the first encoder 11 encodes the 192-bit data output from the first tail bit generator 121 into 576 symbols at the full rate; the second encoder 12 encodes the 96-bit data output from the second tail bit generator 122 into 288 symbols at 1/2 rate; the third encoder 13 encodes the 54-bit data output from the third tail bit generator 123 into 162 symbols at about 1/4 rate; and the fourth encoder 14 encodes the 30-bit data output from the fourth tail bit generator 124 into 90 symbols at about 1/8 rate.
The rate matcher 20 includes repeaters 22-24 and symbol deletion devices 27-28. The repeaters 22-24 repeat symbols outputted from the second to fourth encoders 12-14 at predetermined times in order to increase output symbol rates to the full rate of 576 symbols (or bits). For instance, since the second encoder 12 outputs 288 symbols (=1/2 the 576 symbols outputted from the first encoder 11), the second repeater 22 repeats the received 288 symbols two times to output 576 symbols. The xe2x80x9csecond repeaterxe2x80x9d means that it is the repeater for the second rate (1/2 rate); there is no first repeater. The same numbering system is used for the symbol deletion devices. The symbol deletion devices 27 and 28 delete extra symbols outputted from the repeaters 23 and 24 in order to match the number of symbols at the full rate (i.e., 576). For instance, since the third encoder 13 outputs 162 symbols ( greater than 1/4 the 576 symbols outputted from the first encoder 11), the third repeater 23 repeats the received 162 symbols four times to output 648 symbols which exceeds the full rate of 576 symbols. In order to match the symbol rate to the full rate, the third symbol deletion device 27 deletes every ninth symbol of the 648 symbols to output the full rate of 576 symbols. In addition, since the fourth encoder 14 outputs 90 symbols ( greater than 1/8 the 576 symbols output from the first encoder 11), the fourth repeater 24 repeats the received 90 symbols eight times to output 720 symbols which exceeds the full rate of 576 symbol. To match the symbol rate to the full rate, the fourth symbol deletion device 28 deletes every fifth symbol of the 720 symbols to output the full rate of 576 symbols.
First to fourth channel interleavers 31-34 interleave the symbols of full rate outputted from the first encoder 11, the second repeater 22, the symbol deletion device 27 and the symbol deletion device 28, respectively. As illustrated in FIG. 2, symbol repetition is applied only to the symbols of non-full rate. Here, the carriers A, B and C each have a bandwidth of 1.2288 MHz (about 1.25 MHz), and the whole bandwidth of the three carriers is equal to three IS-95 channel bandwidths. Therefore, the three carriers A, B and C have a bandwidth of 3.6864 MHz in total, which is about 5 MHz. Forward Error Correction (FEC) is used to maintain a sufficiently low Bit Error Rate (BER) for a mobile station channel having a low signal-to-noise ratio (SNR) by providing a channel coding gain. The forward link for the multicarrier communication system can share the same frequency band with the forward link for the IS-95 system by using an overlay method. However, the overlay method provides the following problems.
In the overlay method, three forward link carriers for the multicarrier system are overlaid on three 1.25 MHz bands used in the IS-95 CDMA system. FIG. 3 illustrates the transmission power levels, by the respective bands, of base stations for the IS-95 system and the multicarrier system. In the overlay method, since the frequency bands for the multicarrier-system are overlaid on the frequency bands for the IS-95 system, the transmission power or channel capacity is shared between the IS-95 base station and the multicarrier base station at the same frequency band. This means there are two different base stations. In other words, there is an IS-95 base station and an IMT-2000 base station. In the case where the transmission power is shared between the two systems, the transmission power is first allocated for the IS-95 channel which mainly supports a voice service and then, the maximum transmission power permissible to the respective carriers for the multicarrier CDMA system is determined. However, the maximum transmission power cannot exceed a predetermined power level, because the base station has limited transmission power. Further, when the base station transmits data to many subscribers increasing interference among the subscribers results in an increase in noise. FIG. 3 illustrates the state where the IS-95 base station and the multicarrier base station allocate substantially equal transmission power at the respective 1.25 MHz frequency bands.
However, the IS-95 channels of 1.25 MHz frequency bands have a different transmission power according to a change in the number of subscribers in service and a change in voice activity of the subscribers. FIGS. 4 and 5 illustrate situations where the transmission power allocated for the multicarrier base station decreases at some carrier frequencies, because the transmission power allocated for the IS-95 base station has increased rapidly at those frequency bands due to an increase in the number of IS-95 subscribers. As a result, sufficient transmission power cannot be allocated for one or more of the multiple carriers so the SNRs are different for the respective carriers at the receiver. Accordingly, a signal received at a carrier having the low SNR increases in the bit error rate (BER). That is, when the number of IS-95 subscribers increases and the voice activity is relatively high, the signal transmitted via a carrier overlaid on the corresponding busy frequency band increases in BER, resulting in a decreased system capacity and an increased interference among the IS-95 subscribers. That is, the overlay method may cause capacity reduction in the multicarrier system and an increase in interference among the IS-95 subscribers.
In the multicarrier system, the respective carriers may have independent transmission powers as illustrated in FIGS. 4 and 5. With respect to performance, because only two of the three carriers have sufficient power, FIG. 4 shows a power distribution similar to the case where a R=1/2 channel encoder is used; and, because only one of the three carriers has sufficient power, FIG. 5 shows the power distribution being worse than the case where a channel encoder is not used. In these cases, one or two of the three coded bits (i.e., symbols) for an input data bit may not be transmitted, causing a degradation in system performance.
Therefore, even in a DS-CDMA communication system using a single carrier, weight distribution of the symbols generated by channel encoding is poor, thereby causing a degradation in channel decoding performance. This invention is not limited to DS-CDMA and multicarrier CDMA systems.
It is, therefore, an object of the present invention to provide a channel coding device and method for generating coded data bits having a good channel decoding performance in a DS-CDMA communication system.
It is another object of the present invention to provide a R=1/6 convolutional encoding device and method for increasing a channel performance in a channel transmitter of a DS-CDMA communication system.
To achieve the above objects, there is provided a communication device for a direct sequence code division multiple access (DS-CDMA) communication system. The communication device comprises a CRC (Cyclic Redundancy Code) generator for generating CRC bits according to input data bits and adding the generated CRC bits to the input data bits; a channel encoder for encoding the CRC-added data bits preferably using a coding rate R=1/6 convolutional code of a generator polynomial of (457, 755, 551, 637, 523, 727); and an interleaver for interleaving the coded data bits.
The channel encoder comprises a plurality of delays for delaying the input data bits to output first to eighth delayed data bits; a first operator for exclusively ORing the input data bits and the third, fifth, sixth, seventh and eighth delayed data bits to generate a first symbol; a second operator for exclusively ORing the input data bits and the first, second, third, fifth, sixth and eighth delayed data bits to generate a second symbol; a third operator for exclusively ORing the input data bits and the second, third, fifth and eighth delayed data bits to generate a third symbol; a fourth operator for exclusively ORing the input data bits and the first, fourth, fifth, sixth, seventh and eighth delayed data bits to generate a fourth symbol; a fifth operator for exclusively ORing the input data bits and the first, fourth, sixth and eighth delayed data bits to generate a fifth symbol; and a sixth operator for exclusively ORing the input data bits and the first, second, fourth, sixth, seventh and eighth delayed data bits to generate a sixth symbol.